1. Field of the Invention
The present invention relates to an integrated circuit and fabrication method. More specifically, the present invention relates to an integrated circuit including transistors formed in a plurality of planes on substrates including an oxide-isolated substrate and a silicon substrate.
2. Description of the Related Art
In the past several decades, the semiconductor industry has continuously developed new and improved fabrication processes. Process improvements, including process improvements and structural improvements, have generated more highly integrated and reliable circuits. Manufacturing process improvements and economies of scale resulting in reduced costs and prices have combined to result in fabrication of devices and circuits in increasingly high densities, quantities, and reliability. Structural improvements include new device designs that improve circuit performance, power control, and reliability.
Technological advancements from small-scale integration (SSI) to ultralarge-scale integration (ULSI) are accompanied by a trend to increasing integrated circuit chip size and decreasing size of individual circuit components. Although integrated circuit chip size has grown as increasing numbers of devices are constructed on the chip, higher densities more greatly result from a decrease in the size of each part of the individual devices, known as the device feature size. The decrease in feature size has resulted from technological improvements in photolithography imaging processes and a trend toward fabrication of multiple layers of conductors.
Recently, the improvements in photolithography have slowed due to limitations in the imaging process, which are exacerbated by increased surface steps, additional layers, and increases in wafer diameter.
What is needed is a semiconductor processing technique and integrated circuit structural design that allows for increased improvement in integrated circuit density.